1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and particularly to a nonvolatile memory device capable of performing reading and writing operation at random (referred to hereinafter as a nonvolatile RAM).
2. Description of the Prior Art
In the prior art, an EEPROM is known as an electrically reloadable nonvolatile semiconductor memory device. However, an reprogrammable involves disadvantages that writing operation takes time represented by milliseconds and that the number of reloading operations is limited. For this reason, a conventional nonvolatile RAM is formed by combination of a static RAM cell for high speed reading and writing operation and an EEPROM cell for nonvolatile storage.
FIG. 1 shows an example of an arrangement of the memory cell in a conventional nonvolatile RAM. This memory cell in FIG. 1 is disclosed in ISSCC Digest of Tech. Papers, pp. 170-171, Feb., 1983. Referring to FIG. 1, the memory cell comprises two portions; one is a memory cell portion 1 as a static RAM comprising flip-flop formed by four MOS transistors Q1-Q4, and two transfer gates Q5 and Q6, and the other is a memory cell portion 2 as an EEPROM comprising a floating gate tunnel oxide (FLOTOX) double gate transistor Q7 and two transistors Q8 and Q9. The output end (the drain of the transistor Q2) of the flip-flop is connected to the FLOTOX transistor Q7 through the transfer gate Q8 so that the function of the nonvolatile RAM is performed by transference of the stored content between the two portions 1 and 2. Selection of the memory cell is made by means of a word line WL. More specifically, selection of the word line WL enables the transfer gates Q5 and Q6 to be opened so that data is read out or written through bit lines BL and BL. Nonvolatile storage of data is made by applying appropriate voltage signals to the terminals CLR, PRO and CLK and the power supply line V.sub.DD of the memory cell through the transfer gate Q8 and the transistor Q9.
Thus, the memory cell of the conventional nonvolatile RAM is formed by combination of the memory cell portion as the static RAM and the memory cell portion as the EEPROM and accordingly there are disadvantages that the number of transistors necessary for one memory cell becomes large and the area occupied by one cell is increased, which makes it difficult to improve the integration scale. In addition, the number of signal lines becomes large, which causes the circuit configuration and the operation to be complicated.